diff --git a/src/util.c b/src/util.c index 08f3721..cb90f19 100644 --- a/src/util.c +++ b/src/util.c @@ -34,6 +34,45 @@ #endif #endif +#if defined(__linux__) && defined(__riscv) +#if __has_include() +#include +#else +#include + +#if __has_include() +#include +#include +#else +#define __NR_riscv_hwprobe 258 +struct riscv_hwprobe { + int64_t key; + uint64_t value; +}; +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#endif + +// RISC-V Scalar AES [E]ncryption and [D]ecryption +#ifndef RISCV_HWPROBE_EXT_ZKND +#define RISCV_HWPROBE_EXT_ZKND (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 12) +#endif + +// RISC-V Vector AES +#ifndef RISCV_HWPROBE_EXT_ZVKNED +#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21) +#endif + +static int __riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, + size_t cpu_count, unsigned long *cpus, + unsigned int flags) +{ + return syscall(__NR_riscv_hwprobe, pairs, pair_count, cpu_count, cpus, flags); +} + +#endif +#endif + int write_bool(char *path, bool val) { int fd = open(path, O_RDWR); @@ -90,10 +129,18 @@ bool has_fast_aes() { return __builtin_cpu_supports("aes"); #elif defined(__BUILTIN_CPU_SUPPORTS__) && defined(__powerpc__) return __builtin_cpu_supports("vcrypto"); -#elif defined(__riscv) - // TODO: Implement detection of RISC-V vector crypto extension when possible. - // At the time of writing, no RISC-V hardware has it, so hardcode it off. - return false; +#elif defined(__linux__) && defined(__riscv) + struct riscv_hwprobe pairs[1] = { + { RISCV_HWPROBE_KEY_IMA_EXT_0, 0 }, + }; + + // If this syscall is not implemented, we'll get -ENOSYS + // and the value field will remain zero. + __riscv_hwprobe(pairs, sizeof(pairs) / sizeof(struct riscv_hwprobe), 0, NULL, 0); + + return (pairs[0].value & (RISCV_HWPROBE_EXT_ZKNE | RISCV_HWPROBE_EXT_ZKND)) == + (RISCV_HWPROBE_EXT_ZKNE | RISCV_HWPROBE_EXT_ZKND) || + (pairs[0].value & RISCV_HWPROBE_EXT_ZVKNED); #elif __SIZEOF_SIZE_T__ == 4 #warning Unknown 32-bit platform. Assuming AES is slow on this CPU. return false;